Dynamic Random Access Memory (DRAM) is utilized in modern computing architectures. DRAM may provide advantages of structural simplicity, low cost and high speed in comparison to alternative types of memory.
A memory cell having promise for utilization in DRAM is a memory cell configuration having two transistors and one capacitor (a so-called 2T-1C memory cell configuration). A 2T-1C memory cell is schematically illustrated in FIG. 1 as a memory cell configuration 2. The two transistors of the memory cell are labeled as T1 and T2, and the capacitor of the memory cell is labeled as CAP.
A source/drain region of T1 connects with a first node of the capacitor CAP, and the other source/drain region of T1 connects with a first comparative bitline BL-1. A gate of T1 connects with a wordline WL. A source/drain region of T2 connects with a second node of the capacitor CAP, and the other source/drain region of T2 connects with a second comparative bitline BL-2. A gate of T2 connects with the wordline WL.
The comparative bitlines BL-1 and BL-2 extend to circuitry 4 which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of the memory cell. The circuitry 4 may include a sense amplifier. The comparative bitlines BL-1 and BL-2 are utilized in tandem to address memory cells, and in some aspects may be considered to function together as a single digit line.
A problem that may occur relative to the transistors of the memory cell configuration 2 is described with reference to FIG. 2. The transistor T1 is illustrated together with regions of the wordline WL, the bitline BL-1 and the capacitor CAP, with only a portion of one of the electrical nodes of the capacitor being shown. The transistor T1 includes a vertical pillar 5 of semiconductor material. An insulative material 3 is provided alongside the vertical pillar 5, and over the wordline WL. Regions of the insulative material 3 between the wordline WL and the vertical pillar 5 may correspond to gate dielectric, and may have a different composition than other regions of the insulative material 3.
The insulative material 3 may comprise any suitable composition; including, for example, silicon dioxide.
The vertical pillar 5 may comprise any suitable composition, and in some embodiments may comprise appropriately-doped silicon. The vertical pillar 5 includes a body region 10 of the transistor T1, and includes source/drain regions 14 and 16 of the transistor 10.
The body region 10 is shown to be vertically offset from the source/drain regions 14 and 16, and is between the source/drain regions 14 and 16. An approximate interface between the source/drain region 14 and the body region 10 is illustrated with a dashed line 13, and an approximate interface between the source/drain region 16 and the body region 10 is illustrated with a dashed line 15. The source/drain regions 14 and 16 may be conductively-doped regions of the semiconductor material of vertical pillar 5.
The bitline BL-1 is supported by an insulative material 7. Such insulative material may comprise any suitable composition or combination of compositions; such as, for example, silicon dioxide, silicon nitride, etc.
The transistor T1 is illustrated in two operational modes A and B. The operational mode A has electrical isolation between the capacitor CAP and the bitline BL-1, and the operational mode B has electrical coupling between the capacitor CAP and the bitline BL-1. The operational mode A may correspond to an operational state of the wordline WL in which low voltage, or no voltage, is passed along the wordline. The operational mode B may correspond to an operational state of the wordline WL in which sufficient voltage is passed along the wordline to attract charge carriers to segments of the body region 10 proximate the wordline, and to thereby form conductive channels 12 (illustrated by dashed-lines) along the body region 10 between the source/drain regions 14 and 16. As the source/drain regions 14 and 16 are conductive regions coupled with the bitline BL-1 and the capacitor CAP, respectively, the conductive channels 12 electrically couple the capacitor CAP and the bitline BL-1 with one another.
A problem that may occur relative to the illustrated transistor T1 is that the body region 10 is a floating body. Consequently, a memory cell comprising such transistor (i.e., the memory cell 2) may suffer from floating body effects, which may lead to degraded charge retention, power distribution problems, and/or other problems.
Although not illustrated, the transistor T2 (shown in FIG. 1) may comprise a floating body analogous to the floating body 10 of transistor T1; which may exacerbate the floating body effects of memory cell 2.
It would be desirable to develop memory cell configurations which alleviate the above-discussed floating body effects associated with the transistors T1 and T2, and to develop memory arrays incorporating such memory cell configurations.